Welcome to the Bartels Group of Companies
Allgemeine Hinweise - Deutsche Version General - English Version
Bartels

Bartels System GmbH
Bartels
Bartels AutoEngineer
BAE Product Info
BAE Price List
BAE Downloads
BAE Documentation
BAE Installation Guide
BAE User Manual
Preface
1 Introduction
2 Circuit Design
3 Packager
4 PCB Design
5 IC/ASIC Design
5.1 General
5.1.1 Components and Features
5.1.2 IC Design System Startup
5.1.3 Chip Editor Main Menu
5.1.4 Chip Editor User Interface
5.1.5 Chip Editor System Features
5.2 IC Cell Library
5.3 IC Mask Layout
5.4 Cell Placer
5.5 Cell Router
5.6 IC Design Data
6 Rule System
7 Utilities
BAE Libraries
User Language Programmer's Guide
BAE Update History
BAE Next Version Release Notes Preliminary
BAE V8.0 Release Notes
BAE V7.8 Release Notes
BAE V7.6 Release Notes
BAE V7.4 Release Notes
BAE V7.2 Release Notes
BAE V7.0 Release Notes
BAE V6.8 Release Notes
BAE V6.6 Release Notes
BAE V6.4 Release Notes
BAE V6.2 Release Notes
BAE V6.0 Release Notes
BAE V5.4 Release Notes
BAE V5.0 Release Notes
BAE V4.6 Release Notes
BAE V4.4 Release Notes
BAE V4.2 Release Notes
BAE V4.0 Release Notes
BAE V3.4 Release Notes
BAE Support
BAE Contributions
BAE Development and Service Companies
Electronics Development
Bartels Sport Service
Company Profile
Corporate Info
Bartels :: Bartels AutoEngineer :: BAE Documentation :: BAE User Manual :: IC/ASIC Design :: General
Bartels AutoEngineer® - User Manual

5.1 General

Bartels AutoEngineer® Dokumentation

The Bartels AutoEngineer IC Design system essentially consists of an interactive Chip Editor (IC Mask Editor) with integrated cell/macro symbol editor and comprehensive design rule checking facilities, Cell Placer for automatic standard cell placement, and the Cell Router for automatic IC layout routing. GDS View and CIF View program modules for importing and/or checking cell libraries and/or IC mask data in GDS and/or CIF format are also included in the software.

 

5.1.1 Components and Features

Chip Editor

The floating point database used throughout the BAE Chip Editor allows for the mixed specification of metric (mm, µm) and imperial (Inch, mil) coordinate units. All placement coordinates including rotation angles can be specified with floating point values. There are no restrictions at the definition and placement of pin areas, active areas, cells, traces, texts, etc. The user interface accurately displays even the more complex structures such as circles or arcs.

The Design Rule Check (DRC) operates in grid-free mode with a precision of eight digits behind the decimal point. The DRC provides constant monitoring of connection areas and traces/pins against the net list, with visual indication of distance violations and short-circuits. The system supports both Online and Batch DRC. Online DRC performs incremental checks, i.e., only the modified items are checked real-time thus saving computation time.

The Undo/Redo facilities allow to use the Chip Editor without fear of causing damage. Up to twenty commands can be reversed or undone by applying the Undo function and then reprocessed with the Redo function. Undo/Redo ensures data security and provides a powerful feature for estimating design alternatives.

Arbitrary parts of the chip layout can be selected to groups and then moved, rotated, mirrored, copied or saved (and subsequently used as templates).

Fast interactive cell placement with instant connections update guarantees an optimum exploitation of the chip area. Connections (unroutes, airlines) are dynamically calculated and instantly displayed during placement. Cells can scaled, mirrored and rotated at arbitrary angles. Cells can be placed at arbitrary coordinates and polar coordinates are supported for placing cells on a circle. The cell library supports cell-specific preferences for rotation and mirroring. During manual placement, alternative cell definition (as configured in the cell library) can be selected for the currently processed cell.

The system supports genuine net-orientated Connectivity. This means that electrical connections can be realized through connection areas instead of traces connecting. Traces and connection areas can be created in grid-free mode with floating point precision. Highlight is used to indicate the selected and/or processed signal, and each point of the signal can be connected. The system also supports partial vias with automatic via type selection.

Active areas can be resized using arbitrary expansion values. Trace segment lengths and active area edge lengths can automatically be determined or measured for test or documentation purposes.

With the Bartels User Language integrated to the Chip Editor the user is able to implement enhanced CAD functions and macros, user-specific import and export functions, report and test functions, etc. User Language programs can be called by applying the Run User Script function from the File menu or by pressing a key on the keyboard (hot key).

Cell Placer

Sorry, this information is currently being updated.

Cell Router

The Cell Router is used for automatically routing the traces of the chip layout. The Cellrouter kernel is based on the well-known Bartels AutoEngineer with its highly sophisticated backtracking and rip-up/retry algorithms. These type of routing algorithms are capable of achieving 100% route completion where other routers fail. Extensive artificial intelligence features are built into the router to produce high quality design results in a reasonable time. The Cell Router includes special features for optimizaing the routing for IC mask production. The complete routing process is supervised by a backtracking algorithm. This backtracking prevents from a deterioration of the routing result or a dead-lock during rip-up or optimization and is capable to exploit new and/or better routing solutions.

Both the selective rip-up and the cross-net optimizer passes are assisted by a unique intelligent multi-net cleanup algorithm. This algorithm identifies traces and/or trace segments which are blocking other conncetions and rips up and reroutes multiple connections or even trees at a time to improve the global routing result. The Cell Router is capable of moving trace bunches to make space for not yet routed connections (push'n'shove routing). Cleanup passes for performing cross-net changes are applied during optimization and will considerably reduce via counts and straighten trace paths. All advanced routing features are supported by a sophisticated array of heuristic cost parameters which can be dynamically adapted to produce quality routing results comparable to those made by skilled layout designers.

The Cell Router is capable of simultaneously routing up to 12 layers. The Cell Router automatically identifies and connects pre-placed traces and active connection areas. The routing width is pin-specific rather than net-specific. T-shaped connections are automatically generated (full copper sharing).

The routing progress can be watched both graphically and on statistical readout on the Cell Router user interface. The Cell Router can be stopped at any time and then continued or re-started with changed parameters on demand.

The Cell Router provides features and functions for automatically adapting the chip layout to placement and/or net list changes (re-entrant routing) where the Cell Router evaluates pre-routed traces, identifies and removes wrong and redundant paths and short-circuits, and then (re-)routes open connections to achieve a correct 100% solution. Subsequently, the modified chip layout can be optimized again.

All of today's advanced chip technologies are fully supported by the Cellrouter. The Cellrouter is able to consider and/or connect arbitrarily shaped pin definitions, traces, connection areas and keepout areas. The built-in off-grid recognition allows for the off-grid placement of cells, pins and pre-routed traces. The Cellrouter supports the selection of arbitrary routing grids with optional half-grid routing. The Cellrouter also maintains partial vias with automatic via type selection to increase the routability of chip layouts with more than two layers. Area and block routing methods can be supported by defining keepout routing areas and/or prohibited layers, and the Cellrouter is also able to consider via keepout areas.

GDS View

GDS View is a graphic program for displaying GDS-II files and/or GDS-II file elements for visual checks. An option is provided to select top level structures only or all hierarchy levels when loading GDS-II data. Zoom functions and color assignment facilities are provided for displaying the data once it's loaded. GDS-View provides a function for saving the currently loaded GDS data as standard cell library element to the Bartels AutoEngineer IC Design system and a batch utility for importing GDS-II standard cell libraries to the Bartels AutoEngineer IC Design system.

CIF View

CIF View is a graphic program for displaying CIF files and/or CIF file elements for visual checks. A scaling factor can be set for loading CIF data. Zoom functions and color assignment facilities are provided for displaying the data once it's loaded.

 

5.1.2 IC Design System Startup

Unless you work on a system with multi-windowing and advanced directory and file selection dialogs, it is recommended to start the Bartels AutoEngineer from the directory where the design files should be generated since this considerably simplifies job file access. If you intend to process the examples provided with this manual it is recommended to move to the BAE examples directory baejobs which is installed with the BAE software. The IC Design system can be activated from the Bartels AutoEngineer main menu which can be started from your operating system shell with the following command:

> bae Return/Enter Key (CR)

Modern operating system with multi-windowing support provide more convenient features for activating the BAE main menu. Under Windows, a BAE program group with the BAE Main Menu function for activating the BAE main menu is installed to the Start menu. And it's also not all that important to work from your project directory if your system provides sophisticated file and/or directory selection dialogs.

The BAE Main Menu displays the Bartels logo and the following menu:

Schematic
Layout
[ IC-Design ]
Packager
CAM-View
[ Setup ]
[ Next Task ]
Exit BAE

The Setup function is only available under Windows and/or Motif. The Next Task is only available in BAE HighEnd and BAE IC Design. The IC-Design menu item is only provided with the BAE IC Design system.

Move the menu cursor to the IC-Design menu item and confirm this choice by pressing the left mouse button:

IC-DesignLeft Mouse Button (LMB)

The Chip Editor program module is loaded and the Chip Editor menu is activated. Check your BAE software installation if this fails to happen (see the Bartels AutoEngineer® Installation Guide for details on how to perform a correct installation).

 

5.1.3 Chip Editor Main Menu

Depending on the operating system platform, the Bartels AutoEngineer can be operated with different user interfaces and/or menu configurations.

The standard/sidemenu user interface is available on all platforms and provides a menu area on the right side, consisting of the main menu on top and the currently active menu below that main menu. After entering the Chip Editor the Files menu is active and the menu cursor points to the Load Element function.

The Windows and Motif versions of the Chip Editor can optionally be operated with a pull-down menu user interface providing a horizontally arranged main menu bar on top. The Setup dialog from the BAE main menu can be used to select the desired menu configuration. When selecting the pulldonw menu configuration, the Menu type/Mouse Mode option also provides a choice for assigning repeat function and the context popup menu to the right and left or left and right mouse buttons.

The Chip Editor main menu is always available and provides the following menus and/or functions:

Undo, Redo
Display
Files
Macros
Traces
Areas
Text
Groups
Parameter
Utilities

Undo, Redo

The functions provided with the Undo, Redo menu allow you to use the Chip Editor without fear of causing damage. Up to twenty commands can be reversed or undone using Undo and then reprocessed with the Redo. This is true even for complex processing such as group functions or User Language program execution. Undo, Redo ensures data security and provides a powerful feature for estimating design alternatives.

Display

The View or Display menu can either be activated by selecting the corresponding main menu item or by pressing the middle mouse button. Activation through the middle mouse button is even possible whilst performing a graphical manipulation such as placing or moving an object. The View or Display menu provides useful functions for changing display options such as zoom window, zoom scale, input and/or display grids, grid and/or angle lock, color settings, etc. The View or Display menu also contains advanced display functions such as Find Part and Query Element.

Files

The Files menu provides functions for creating, loading, saving, copying, replacing and deleting DDB elements. The Files menu also allows to load and/or store color tables or to call important database management functions such as listing DDB file contents and performing library update.

Macros

The Macros provides functions for manual cell placement, for cell renaming and for manual optimization (component swap, pin/gate swap). The function for selecting the via(s) for subsequent routing is also provided in this menu.

On cell level, the Macros menu is used for placing, moving, deleting and renaming pins.

Traces

The Traces menu provides functions for interactive routing, i.e. for manually creating new traces and for modifying or deleting existing traces and/or trace segments.

Areas

The Areas menu is used for defining the chip outline, for generating connection areas and for creating documentary lines and/or documentary areas. Existing areas can be moved, rotated, mirrored, copied and deleted.

Text

The Text menu is used for creating, moving, changing and deleting texts on any layout hierarchy level.

Groups

The Groups menu provides functions for selecting elements to group, for moving, rotating, mirroring, scaling, copying, deleting, fixing, releasing, saving and loading groups, and for replacing symbols in a group.

Parameter

The Parameter menu provides functions for selecting the layout library, setting the origin and the element boundaries of the currently loaded element, selecting the mincon function for the airline display and activating the automatic design data backup feature.

Utilities

The Utilities menu provides functions for exiting BAE, returning to the BAE main shell, calling the Cell Placer, the Cell Router or GDS View, starting the Batch DRC, displaying a status Report and starting User Language programs.

 

5.1.4 Chip Editor User Interface

Menu Assignments and Key Bindings

The BAE software comes with User Language programs for activating a modified Chip Editor user interface with many additional functions (startups, toolbars, menu assignments, key bindings, etc.). The bae_st User Language program is automatically started when entering the Chip Editor. bae_st calls the uifsetup User Language program which activates predefined Chip Editor menu assignments and key bindings. Menu assignments and key bindings can be changed by modifiying and re-compiling the uifsetup source code. The hlpkeys User Language program is used to list the current key bindings. With the predefined menu assignments of uifsetup activated, hlpkeys can be called from the Key Bindings function of the Help menu. Menu assignments and key bindings can be listed with the uifdump User Language program. The uifreset User Language program can be used to reset all currently defined menu assignments and key bindings. uifsetup, uifdump and uifreset can also be called from the menu of the keyprog User Language program which provides additional facilities for macro programming, online key assignments, and menu programming and menu configuration.

Sorry, this information is currently being updated.

 

5.1.5 Chip Editor System Features

Sorry, this information is currently being updated.

Net List

A net list is usually required for the design of the chip layout. In BAE, the net list is commonly created with the Schematic Editor and then transferred to the IC Design system using the Packager. Alternatively, ASCII net lists can be imported to the AutoEngineer system using the netconv utility program or customized User Language programs. See chapter 3 of this manual for more details on net list processing.

The function for loading a chip layout will not only load the pertinent data from the lower hierarchy levels (cells and pins), but also the corresponding net list. The net list data is correlated with all geometrical data on the chip layout ("Connectivity Generation"). Please note that the element names for both the chip layout and the net list must be identical for this to work.

After successfully generating the connectivity, the system is capable of instantly controlling and/or correlating each layout modification with the net list definitions. This highly sophisticated design feature is called "True Connectivity" and enables real-time recognition of electrical connections, no matter whether connections are created through traces, connection areas or vias. I.e., the system supports advanced routing features such as cross connection recognition, genuine T-connections, lining up traces created with group copying, implementing connections with arbitrarily shaped connection areas, etc.

Sorry, this information is currently being updated.

Bartels :: Bartels AutoEngineer :: BAE Documentation :: BAE User Manual :: IC/ASIC Design :: General

General
© 1985-2017 Oliver Bartels F+E • Updated: 11 October 2010, 10:30 [UTC]

© 1985-2017 Oliver Bartels F+E Bartels Homepage Contact and Corporate Info

Web Development by Baumeister Mediasoft Engineering

Allgemeine Hinweise - Deutsche Version General - English Version